Memory tester and method of switching the tester to RAM test mode and ROM test mode

ABSTRACT

The circuit arrangement of a memory testing apparatus having a ROM expected value memory is simplified. There are provided a first logical comparator 26 for logically comparing a data read out of a memory under test 200 with an expected value data from a pattern generator 11 as well as a second logical comparator 28 having its one input terminal supplied with a result of the comparison in the first logical comparator 26. The second logical comparator 28 has the other input terminal to be supplied with a ROM expected value data read out of a ROM expected value memory 16. A data read out of a RAM under test is logically compared in the first logical comparator 26 while a data read out of a ROM under test is logically compared in the second logical comparator 28.

TECHNICAL FIELD

The present invention relates to a memory testing apparatus providedwith a ROM (read only memory) expected value memory, which is capable oftesting both a writable/readable memory called RAM (random accessmemory) and a read only memory called ROM, and to a method of switchingthe operation mode of the testing apparatus between a RAM test mode anda ROM test mode.

BACKGROUND ART

A memory testing apparatus for testing a writable/readable memory(hereinafter referred to as RAM) generally comprises a timing generator,a pattern generator, a waveform generator, a logical comparator and afailure analysis memory. As is well known, a RAM and a read only memory(hereinafter referred to as ROM) are often formed as a semiconductorintegrated circuit element. In the following description, in order tofacilitate understanding of the present invention, a case will bediscussed in which a memory as constructed in the form of asemiconductor integrated circuit element (hereinafter referred to as ICmemory) is tested by such memory testing apparatus, but it is to benoted that the memory testing apparatus can also test memories otherthan IC memories.

A pattern generator is operative, in response to a reference clock(operating clock) fed from the timing generator, to generate addresspattern data, test pattern data, control signals and the like which areto be applied to an IC memory to be tested (memory under test), and alsoto generate expected value pattern data and the like which are to besupplied to the logical comparator.

An IC memory to be tested (commonly called MUT (memory under test)) iscontrolled in writing of a test pattern signal therein or reading of atest pattern signal therefrom by application of a control signalthereto. Specifically, when a writing control signal is applied to theIC memory under test, a test pattern signal is successively written inthe IC memory under test at an address thereof specified by an addresspattern signal, and when a reading control signal is applied to the ICmemory under test, the test pattern signal previously written in the ICmemory under test is successively read out thereof at an addressspecified by an address pattern signal.

A response output signal read out of the IC memory under test(hereinafter, also referred to simply as memory under test) is suppliedto the logical comparator where it is logically compared with anexpected value pattern data outputted from the pattern generator. If aresult of the comparison indicates that there is an anti-coincidence ora mismatch therebetween, the logical comparator outputs a defectivesignal representing the anti-coincidence, namely, so-called failuredata. Usually, as the failure data is outputted logical "1" which is ahigh logical level (logic H). By contrast, if a result of the comparisonindicates that they coincide with each other, the logical comparatoroutputs a conforming or defectless signal representing the coincidence,namely, so-called pass data. Since the failure data is represented bylogical "1", as the pass data is outputted logical "0" which is a lowlogical level (logic L). The failure data is fed to and stored in thefailure analysis memory.

The failure analysis memory has the same operating rate or speed andstorage capacity as those of the memory under test, and the same addresspattern signal as that applied to the memory under test is applied tothe failure analyses memory. In addition, the failure analysis memory isinitialized prior to the start of a test. For example, when initialized,the failure analysis memory has data of logical "0s" written in all ofthe addresses thereof. Every time a failure data is generated from thelogical comparator during a test of a memory under test, a failure dataof logical "1" is written in the address of the failure analysis memoryspecified by the address pattern signal. That is, in a memory cell ofthe failure analysis memory having the same address as that of thefailure memory cell of the memory under test is written the failure data(logical "1") indicating that failure memory cell of the memory undertest.

Upon completion of one test cycle, a decision is rendered as to whetherthe memory under test is pass or failure in consideration of the numberof failure data stored in the failure analysis memory, the locationswhere failure data occurred, and the like. By way of example, in case ofutilizing the failure data stored in the failure analysis memory forpurpose of relieving a defective memory cell of the memory under test,failure data read out of the failure analysis memory (informationrelating to the locations of defective memory cells of the memory undertest) are totalled, and it is then determined based on the totalledfailure data whether or not the locations of the detected failure memorycells can be relieved by relief means provided in the memory under test.

By contrast, when testing a ROM, test pattern data cannot be written inthe ROM under test. Accordingly, there is provided a ROM expected valuememory (constructed by a ROM) in which was previously stored the samedata as the data which has previously written in the ROM under test, andthe data read out of the ROM under test is logically compared with theexpected value pattern data read out of the ROM expected value memory inthe logical comparator which outputs a failure data in the event aresult of the comparison indicates that there is an anti-coincidence ora mismatch therebetween.

FIG. 3 is a block diagram schematically showing the construction of aconventional memory testing apparatus provided with a ROM expected valuememory. This memory testing apparatus is arranged to be capable oftesting both a RAM and a ROM.

Referring to FIG. 3, the memory testing apparatus 100 comprises a timinggenerator 20 for generating a reference clock (operating clock) whichcontrols the operation of various parts or components, a patterngenerator 11 for outputting address pattern data, test pattern data,expected value pattern data and the like, an address waveform generator21 for generating an address pattern signal having a real waveformcorresponding to an input address pattern data, a data waveformgenerator 22 for generating a test pattern signal having a real waveformcorresponding to an input test pattern data, a driver 23 for applyingthe address pattern signal of real waveform generated from the addresswaveform generator 21 to an IC memory under test 200, a driver 24 forapplying the test pattern signal of real waveform generated from thedata waveform generator 22 to the IC memory under test 200, an analogcomparator 25 for determining whether or not a response output signalread out of the IC memory under test 200 in the form of logic level hasa given voltage value, a logical comparator 26 for logically comparingdata of the comparison result outputted from the analog comparator 25with an expected value pattern data supplied from the pattern generator11, and a failure analysis memory 27 for storing a failure dataoutputted from the logical comparator 26 each time both the data do notcoincide with each other in the logical comparator, the failure databeing stored in a memory cell of the failure analysis memory 27 at theaddress position specified by an address pattern data supplied from thepattern generator 11.

The pattern generator 11 comprises a controller 12 to which thereference clock is supplied from the timing generator 20 and whichcontrols the timing generator 20, an address pattern generator 13controlled by the controller 12 for generating address pattern data, atest pattern generator 14 controlled by the controller 12 for generatingtest pattern data, expected value pattern data and the like, a ROMexpected value memory 16 for generating expected value pattern data fortesting a ROM in a ROM testing mode in which ROMs are to be tested, aswitching circuit 15 for supplying the test pattern data and theexpected value pattern data generated from the test pattern generator 14to the data waveform generator 22 and to the logical comparator 26respectively in a RAM testing mode in which RAMs are to be tested aswell as supplying the ROM testing expected value pattern data read outof the ROM expected value memory 16 to the logical comparator 26 in theROM testing mode, a first delay circuit 18A for delaying the addresspattern data outputted from the address pattern generator 13 by a giventime interval D1, and a second delay circuit 18B for delaying the testpattern data outputted from the test pattern generator 14 by the sametime interval D1.

Further, in the illustrated example, the arrangement is such that theoperation of the data waveform generator 22 is inhibited in the ROMtesting mode whereby only an address pattern signal is applied to the ICmemory under test 200 (ROM).

As stated above, in order to test two kinds of memories, namely, a RAMand a ROM, heretofore, the ROM expected value memory 16 has beenprovided on the input side of the switching circuit 15 so that theswitching circuit 15 can select either of the RAM testing test patterndata and expected value data generated from the test pattern generator14 or the ROM testing expected value pattern data read out of the ROMexpected value memory 16 to supply it to the data waveform generator 22and the logical comparator 26.

Specifically, in the ROM testing mode, the address pattern dataoutputted from the address pattern generator 13 is applied to the ROMexpected value memory 16 thereby to read the ROM testing expected valuepattern data therefrom which is in turn outputted to the logicalcomparator 26 through the switching circuit 15.

To enable the memory testing apparatus to test a plurality of kinds ofROMs, the ROM expected value memory 16 is constructed by a RAM and thesame data as that previously stored in a ROM under test has been writtenin this RAM. However, it should be understood that the ROM expectedvalue memory 16 may be constructed by a ROM. The ROM expected valuememory 16 involves a time lag or delay by nature between the time thatthe memory 16 is accessed and the time that the accessed data is readout thereof. Assuming that this time delay is represented by D1, unlessthe address pattern data supplied from the address pattern generator 13to the address waveform generator 21 is delayed by the same timeinterval D1, the ROM testing expected value pattern data read out of theROM expected value memory 16 and this address pattern data can not befed in the same phase with each other to the logical comparator 26 andthe address waveform generator 21.

In order to delay the address pattern data by the time interval D1, ifthe first delay circuit 18A having the time delay of D1 is inserted in atransmission path 17A for the address pattern data, it results in thatthe phase of a test pattern data supplied from the test patterngenerator 14 to the data waveform generator 22 in the RAM testing modediffers from that of the address pattern data. Therefore, it becomesnecessary to connect the second delay circuit 18B having the same timedelay of D1 in a transmission path 17B for the test pattern data.

Thus, when the circuit arrangement shown in FIG. 3 is taken, the firstdelay circuit 18 and the second delay circuit 18B having the same timedelay must be inserted in the transmission path 17A for the addresspattern data and in the transmission path 17B for the test pattern data,respectively.

In addition, assuming that a delay time is represented by D2, which is atime interval from the time point that an address pattern data isinputted to the input terminal of the address waveform generator 21,followed by that a data is read from the IC memory under test 200 at thecorresponding address and that the read data is fed to the logicalcomparator 26 through the analog comparator 25, and to the time pointthat a failure data is supplied to the input side of the failureanalysis memory 27 (shown in FIG. 3 by a bold solid line with an arrow),an address pattern data directly applied from the address patterngenerator 13 to the failure analysis memory 27 must be delayed by a timeinterval of D1+D2 in order to make the address pattern data in phasewith the failure data applied to the failure analysis memory 27, whereD1 represents the time delay caused by the transmission path 17A for theaddress pattern data

Accordingly, it is necessary to insert a third delay circuit 18C havinga time delay of (D1+D2) in a transmission path from the address patterngenerator 13 to the failure analysis memory 27, as shown in FIG. 3.

It is to be understood that when an address pattern signal is applied tothe address waveform generator 21 to read data from the IC memory undertest 200, the expected value pattern data from the test patterngenerator 14 or the expected value pattern data from the ROM expectedvalue memory 16, one of which is outputted from the switching circuit 15to the logical comparator 26, is normally matched in the logicalcomparator 26 in its phase with the phase of a data read out of the ICmemory under test 200 and inputted to the logical comparator 26, andaccordingly, an associated delay circuit is not shown. Obviously, adelay circuit may be used to match the phase of the expected valuepattern data with the phase of the data read out of the IC memory undertest 200 and inputted to the logical comparator 26.

Thus it will be seen that in the conventional memory testing apparatus100 provided with the ROM expected value memory 16, there is a need toprovide the first delay circuit 18A, the second delay circuit 18B andthe third delay circuit 18C. The setting of the time delay in each ofthese delay circuits requires a troublesome operation because theirrelative time delay must be accurately defined, resulting in adisadvantage that the circuit arrangement becomes complicated. Inaddition, even though the time delays have been set up once, there arecases that the time delays may be varied due to change in temperature,with the lapse of time and the like, and hence a disadvantage occursthat much time and labor are required in its maintenance.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a memory testingapparatus provided with a ROM expected value memory in which itsmanufacture and maintenance are easy.

It is another object of the present invention to provide a method ofswitching the operation mode of a memory testing apparatus provided witha ROM expected value memory between a RAM testing mode and a ROM testingmode by which the manufacture of the testing apparatus can be made easyand the circuit arrangement thereof can be simplified.

According to a first aspect of the present invention, in order toaccomplish the above first object, there is provided a memory testingapparatus which comprises: a pattern generator for outputting at leastan address pattern data and a test pattern data; a waveform generatorfor converting the address pattern data and the test pattern dataoutputted from the pattern generator into an address pattern signal anda test pattern signal each having a real waveform; means for applyingthe address pattern signal and the test pattern signal outputted fromthe waveform generator to a memory under test; a ROM expected valuememory for outputting a ROM expected value pattern data in a ROM testingmode; a first logical comparator for logically comparing a data read outof the memory under test with an expected value pattern data outputtedfrom the pattern generator in a RAM testing mode; a second logicalcomparator for logically comparing a result of the logical comparison inthe first logical comparator with a data outputted from the ROM expectedvalue memory; and a failure analysis memory having the same address areaas that of the memory under test for storing a failure data outputtedfrom the second logical comparator at the same address as that of amemory cell in the memory under test where a failure has occurred, andwherein in the RAM testing mode, fixed data all bits of which have thesame logic are outputted from the ROM expected value memory to besupplied to the second logical comparator, and in the ROM testing mode,fixed data all bits of which have the same logic are outputted from thepattern generator to be supplied to the first logical comparator.

In a preferred embodiment, the memory testing apparatus furthercomprises an analog comparator for determining whether or not thelogical value of a response output signal read out of the memory undertest has a given voltage value, and a data of the comparison result inthe analog comparator is supplied to the first logical comparator.

In addition, the memory testing apparatus further comprises mode settingmeans which serves to supply, in the RAM testing mode, fixed data allbits of which have the same logic from the ROM expected value memory tothe second logical comparator, and to supply, in the ROM testing mode,fixed data all bits of which have the same logic from the patterngenerator to the first logical comparator.

In another preferred embodiment, there are provided pattern generatorset-up means or programming means for setting or programming the patterngenerator so that a predetermined pattern data is generated from thepattern generator and control means for controlling to supply fixed dataall bits of which have the same logic from the ROM expected value memoryto the second logical comparator in the RAM testing mode, and in the ROMtesting mode, the pattern generator set-up means or programming meanscauses the pattern generator to generate fixed data all bits of whichhave the same logic and the control means causes the ROM expected valuememory to generate a ROM expected value pattern data previously writtenin the ROM expected value memory therefrom.

In a further preferred embodiment, the pattern generator is set orprogrammed in the RAM testing mode such that a predetermined patterndata is generated from the pattern generator as well as fixed datapreviously written in the ROM expected value memory, all bits of whichhave the same logic, are generated from the ROM expected value memory,and the pattern generator is set or programmed in the ROM testing modesuch that fixed data all bits of which have the same logic are generatedfrom the pattern generator as well as a ROM expected value pattern datapreviously written in the ROM expected value memory is outputtedtherefrom.

Each of the first and the second logical comparators outputs logical "0"when both the inputs thereto coincide with each other and outputslogical "1" when both the inputs thereto do not coincide with eachother. In addition, the fixed data outputted from the ROM expected valuememory, all bits of which have the same logic, comprise logical "0s" inthe RAM testing mode, and the fixed data outputted from the patterngenerator, all bits of which have the same logic, also comprise logical"0s" in the ROM testing mode.

Further, a first delay circuit is inserted in a transmission path for anaddress pattern data supplied from the pattern generator to the failureanalysis memory, and a second delay circuit is inserted in atransmission path for an address pattern data supplied from the patterngenerator to the ROM expected value memory, and the first delay circuithas a delay time substantially equal to a time interval from the timepoint that an address pattern data is supplied to the waveform generatoruntil the time point that a data read out of the memory under test islogically compared in the first logical comparator and a result of thelogical comparison is outputted therefrom, and the second delay circuithas a delay time equal to a time interval in which a time duration takenfrom the time point that the ROM expected value memory is accessed andto the time point that the stored data is read out thereof is subtractedfrom the delay time of the first delay circuit.

With the construction described above, the ROM testing expected valuepattern data read out of the ROM expected value memory is applied aloneonly to the second logical comparator, and no other signal istransmitted on the signal path on which the expected value pattern datapropagates. Accordingly, a time delay associated with reading of the ROMexpected value memory has no influence upon other signals, and hence itis unnecessary to provide any delay circuit in the pattern generator.

In this manner, no delay circuit is needed to be provided intransmission paths on which an address pattern data and a test patterndata propagate respectively in the RAM testing mode, and thus, thenumber of delay circuits used can be reduced, and the setting and thecontrol of delay times can be made easy. In addition, the maintenancecan also be facilitated.

According to a second aspect of the present invention, in order toaccomplish the above second object, there is provided a method ofswitching the memory testing apparatus constructed as stated abovebetween the RAM testing mode and the ROM testing mode, which comprisesthe steps of: setting or programming the pattern generator so that apredetermined pattern data is generated from the pattern generator; andpreviously writing a predetermined data in the ROM expected valuememory, and the testing apparatus is switched in the operation mode toone of the RAM testing mode and the ROM testing mode by combination ofthe setting or programming of the pattern generator and the datapreviously written in the ROM expected value memory.

In a preferred specific embodiment, in the RAM testing mode, fixed dataall bits of which have the same logic are previously written in the ROMexpected value memory as well as a RAM testing pattern data is generatedfrom the pattern generator by the setting of the pattern generator, andin the ROM testing mode, a ROM testing pattern data is previouslywritten in the ROM expected value memory as well as fixed data all bitsof which have the same logic are generated from the pattern generator bythe setting of the pattern generator.

In another preferred specific embodiment, in the RAM testing mode, fixeddata all bits of which have the same logic are previously written in theROM expected value memory as well as a RAM testing pattern data isgenerated from the pattern generator by the program, and in the ROMtesting mode, a ROM testing pattern data is previously written in theROM expected value memory as well as fixed data all bits of which havethe same logic are generated from the pattern generator by the program.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically showing the construction of anembodiment of the memory testing apparatus according to the presentinvention;

FIG. 2 is a diagram explaining the operation of the main parts of thememory testing apparatus shown in FIG. 1; and

FIG. 3 is a block diagram showing an example of the conventional memorytesting apparatus provided with a ROM expected value memory.

BEST MODE OF CARRYING OUT THE INVENTION

An embodiment of the present invention will now be described in detailwith reference to FIGS. 1 and 2.

FIG. 1 is a block diagram schematically showing the construction of oneembodiment of the memory testing apparatus according to the presentinvention. In FIG. 1, elements, circuits and parts corresponding tothose in the memory testing apparatus shown in FIG. 3 have the samecharacters attached thereto and the explanation thereof will be omittedunless necessary.

In this embodiment, an address pattern data generated from an addresspattern generator 13 is directly fed to an address waveform generator21, and a test pattern data generated from a test pattern generator 14is directly fed to a data waveform generator 22 and a logical comparator26 (hereinafter referred to as first logical comparator). Accordingly,there is provided no delay circuit in a transmission path 17A for theaddress pattern data and a transmission path 17B for the test patterndata.

A second logical comparator 28 is provided on the output side of thefirst logical comparator 26, and has one input terminal to which a dataof a result of the logical comparison in the first logical comparator 26is inputted and the other input terminal to which an expected valuepattern data for testing ROM read out of a ROM expected value memory 16is inputted.

An output from the second logical comparator 28 is fed to a failureanalysis memory 27 thereby storing a final failure data therein. Anaddress pattern data from the address pattern generator 13 is fed to thefailure analysis memory 27 through a third delay circuit 18C having adelay time of D2, and is also fed to a ROM expected value memory 16through a fourth delay circuit 18D having a delay time of (D2-D1). It isto be noted that the delay time D1 corresponds to a time interval takenfrom the time point that the ROM expected value memory 16 is accessedand to the time point that the stored data is read out thereof, and thedelay time D2 corresponds to a time interval taken from the time pointthat an address pattern data is inputted to the input terminal of theaddress waveform generator 21, followed by that a data is read from theIC memory under test 200 at the corresponding address and that the readdata is fed to the first logical comparator 26 through the analogcomparator 25, and to the time point that a failure data is outputted tothe output terminal of the first logical comparator 26 (shown in FIG. 1by a bold solid line with an arrow) shown by a thick solid line with anarrow in FIG. 1.

Like the conventional memory testing apparatus discussed previously,when an address pattern signal is applied to the address waveformgenerator 21 to read data from the IC memory under test 200, theexpected value pattern data supplied from the test pattern generator 14to the first logical comparator 26 is normally matched in the logicalcomparator 26 in its phase with the phase of a data read out of the ICmemory under test 200 and inputted to the logical comparator 26, andaccordingly, an associated delay circuit is not shown. It is needless tosay that a delay circuit may be used to match the phase of the expectedvalue pattern data with the phase of the data read out of the IC memoryunder test 200 and inputted to the first logical comparator 26.

The pattern generator 11 further includes a mode set-up means 19 whichapplies control signals to the test pattern generator 14 and the ROMexpected value memory 16 to control the pattern generation therefrom inaccordance with the testing mode. Specifically, in the RAM testing mode,the test pattern generator 14 generates, in response to a control signalsupplied from the mode set-up means 19 thereto, a RAM testing testpattern data which is then fed to the data waveform generator 22.However, a control signal supplied from the mode set-up means 19 to theRAM expected value memory 16 inhibits the stored data in the memory 16from being read out thereof and hence the memory 16 outputs data allbits of which have a fixed logic of either logical "1" or logical "0" tothe second logical comparator 28. In the following description, thisembodiment will be discussed assuming that the RAM expected value memory16 outputs the data all bits of which have a fixed logic of logical "0"to the second logical comparator 28.

On the other hand, in the ROM testing mode, a control signal suppliedfrom the mode set-up means 19 to the test pattern generator 14 inhibitsthe test pattern generator 14 from generating a test pattern datatherefrom, and then the test pattern generator 14 outputs data all bitsof which have a fixed logic of logical "0" in this example to the firstlogical comparator 26. In contrast, a control signal supplied from themode set-up means 19 to the ROM expected value memory 16 enables thestored data in the memory 16 to be read out of the memory 16. As aresult, the stored data in the memory 16 is read out in accordance withan address pattern data supplied from the address pattern generator 13to the ROM expected value memory 16 to be outputted to the secondlogical comparator 28.

FIG. 2 shows a truth table listing all possible combinations of testpattern data, data read out of the memory under test 200 (which is ROMin this example), and data read out of the ROM expected value memory 16.Each of the first and the second logical comparators 26 and 28 outputslogical "0" whenever both the input data thereto coincide with eachother, and outputs logical "1" whenever both the input data thereto donot coincide with each other.

In FIG. 2, a portion of the truth table corresponding to test timingsT1-T4 indicates all possible combinations which occur when the testpattern data represents logical "0" while the rest of the truth tablecorresponding to the test timings T5-T8 indicates all possiblecombinations which occur when the test pattern data is logical "1".

As shown in FIG. 2, if a data read out of the memory under test 200(which is ROM in this example) is logical "0" at test timing T1, boththe input data coincide with each other, and hence a temporary failuredata outputted from the first logical comparator 26 is logical "0". Ifdata read out from the ROM expected value memory 16 is logical "0", thetemporary failure data is also logical "0", and hence a final failuredata outputted from the second logical comparator 28 is also logical "0"representing the coincidence between both the data.

At test timing T2, when a data read out of the memory under test 200 islogical "1", both the input data do not coincide with each other, andhence the first logical comparator 26 outputs a temporary failure dataof logical "1". If a data read out of the ROM expected value memory 16is logical "0", the final failure data will be logical "1" representingthe anti-coincidence between both the data since the temporary failuredata is logical "1".

At test timing T3, when a data read out of the memory under test 200 islogical "0", both the input data coincide with each other, and hence thefirst logical comparator 26 outputs a temporary failure data of logical"0". If a data read out of the ROM expected value memory 16 is logical"1", the final failure data will be logical "1" representing theanti-coincidence between both the data since the temporary failure datais logical "0".

At test timing T4, when a data read out of the memory under test 200 islogical "1", both the input data do not coincide with each other, andhence the first logical comparator 26 outputs a temporary failure dataof logical "1". If a data read out of the ROM expected value memory 16is logical "1", the final failure data will be logical "0" representingthe coincidence between both the data since the temporary failure datais logical "1".

At test timing T5, when a data read out of the memory under test 200 islogical "0", both the input data do not coincide with each other, andhence the first logical comparator 26 outputs a temporary failure dataof logical "1". If a data read out of the ROM expected value memory 16is logical "0", the final failure data will be logical "1" representingthe anti-coincidence between both the data since the temporary failuredata is logical "1".

At test timing T6, when a data read out of the memory under test 200 islogical "1", both the input data coincide with each other, and hence thefirst logical comparator 26 outputs a temporary failure data of logical"0". If a data read out of the ROM expected value memory 16 is logical"0", the final failure data will be logical "0" representing thecoincidence between both the data since the temporary failure data islogical "0".

At test timing T7, when a data read out of the memory under test 200 islogical "0", both the input data do not coincide with each other, andhence the first logical comparator 26 outputs a temporary failure dataof logical "1". If a data read out of the ROM expected value memory 16is logical "1", a result of the comparison in the second logicalcomparator 28 will be logical "0" representing the coincidence betweenboth the data since the temporary failure data is logical "1".

At test timing T8, when a data read out of the memory under test 200 islogical "1", both the input data coincide with each other, and hence thefirst logical comparator 26 outputs a temporary failure data of logical"0". If a data read out of the ROM expected value memory 16 is logical"1", the second logical comparator 28 will output logical "1"representing the anti-coincidence between both the data since thetemporary failure data is logical "0".

As discussed above, in the ROM testing mode, any test pattern data (orexpected value pattern data) is logical "0" at every test timing.Accordingly, the test timings T1 to T4 can be used in the ROM testingmode. The test timings T1 and T2 can also be used in the RAM testingmode since the output data from the ROM expected value memory 16 in thetest timings T1 and T2 are logical "0s".

On the other hand, in the test timings T5-T8, any test pattern data islogical "1", and hence the test timings T5-T8 cannot be used in the ROMtesting mode. Since the test pattern data in the RAM testing mode is apattern data in which logical "1" and logical "0" are combined in apredetermined sequence, there is a possibility that the test timingsT5-T8 can be used in the RAM testing mode. However, in the RAM testingmode, the output data from the ROM expected value memory 16 has alogical level fixed to logical "0" at every test timing as mentionedpreviously. Accordingly, only the test timings T5 and T6 can be used inthe RAM testing mode.

Test timings T7 and T8 in which the test pattern data is logical "1" andthe output data from the ROM expected value memory 16 is also logical"1" represent a state which cannot be set in practice, and obviouslycannot be used in the RAM testing mode.

Further, in the embodiment described above, the mode set-up means 19 isprovided to apply control signals to the test pattern generator 14 andthe ROM expected value memory 16 respectively thereby switching theoperation mode of the memory testing apparatus between the ROM testingmode and the RAM testing mode. However, it is possible to switch theoperation mode of the memory testing apparatus between the ROM testingmode and the RAM testing mode without providing the mode set-up means19. An example thereof will be described below.

The pattern generator 11 is normally arranged in the RAM testing mode soas to generate a predetermined test pattern data by previously settingthe pattern generator 11 or a program. On the other hand, as statedabove, the same data as the data stored in the memory under test ispreviously written in the ROM expected value memory 16, and accordingly,a combination of the setting of the pattern generator 11 or a programfor operating the pattern generator 11 and the data previously writtenin the ROM expected value memory 16 may be used to switch between thetest timings T1-T4 (ROM testing mode) and T1, T2, T5 and T6 (RAM testingmode) as illustrated in FIG. 2, for instance.

For example, if the pattern generator 11 may be set or a program foroperating the pattern generator 11 may be prepared in the ROM testingmode such that the test pattern data (or expected value pattern data) oflogical "0" is generated at any test timing and control means may causedata previously written in the ROM expected value memory 16 to beoutputted therefrom, and in the RAM testing mode, the control means maycause data of logical "0" to be outputted from the ROM expected valuememory 16 and the pattern generator 11 may be set or a program foroperating the pattern generator 11 may be prepared so that apredetermined test pattern data and an expected value pattern data inwhich logical "0" and logical "1" are combined can be generated, it ispossible to switch between the ROM testing mode and the RAM testing modewithout providing the mode set-up means 19.

Alternatively, if the pattern generator 11 may be set or a program foroperating the pattern generator 11 may be prepared in the ROM testingmode such that the test pattern data (or expected value pattern data) oflogical "0" is generated at any test timing and the same data as thedata previously written in the memory under test may be generated fromthe ROM expected value memory 16, and in the RAM testing mode, thepattern generator 11 may be set or a program for operating the patterngenerator 11 may be prepared so that a predetermined test pattern dataand an expected value pattern data in which logical "0" and logical "1"are combined can be generated and fixed data previously written in theROM expected value memory 16, all bits of which are logical "0", may begenerated from the ROM expected value memory 16, it is no need forproviding a separate mode set-up means in the memory testing apparatus.

Generally speaking, the latter technique is more frequently adopted(only the pattern generator 11 is set or programmed and fixed data allbits of which have the same logic or the same data previously written inthe ROM expected value memory 16 as the data stored in the memory undertest is generated from the ROM expected value memory 16 depending on themode).

As described above, the memory testing apparatus according to thepresent invention operates in the ROM testing mode such that expectedvalue pattern data supplied from the test pattern generator 14 to thefirst logical comparator 26 are fixed to logical "0" in all bits, alldata read out of the memory under test 200 (ROM) are sequentiallycompared with logical "0" in the first logical comparator 26 which inturn outputs temporary failure data as the comparison results, thetemporary failure data are sequentially compared with normal expectedvalue pattern data read out of the ROM expected value memory 16 in thesecond logical comparator 28, and then correct final failure data areobtained from the second logical comparator 28. In the RAM testing mode,the memory testing apparatus operates such that data read out of thememory under test 200 (RAM) are sequentially compared with normalexpected value pattern data supplied from the test pattern generator 14in the first logical comparator 26, and the comparison results aresequentially compared with data all bits of which are logical "0" in thesecond logical comparator 28. In this instance, the comparison resultsof in the second logical comparator 28 becomes the same as thecomparison results in the first logical comparator 26, and hence it willbe understood that correct failure data can be also obtained in the RAMtesting mode.

In accordance with the present invention, a method of switching theabove-described memory testing apparatus between the ROM testing modeand the RAM testing mode can be provided by utilizing a combination ofthe set-up of the pattern generator 11 or a program for operating thepattern generator 11 and data previously written in the ROM expectedvalue memory 16.

As described above, in accordance with the present invention, there areno need for providing delay circuits in the test pattern generator, andhence a cumbersome operation or works required for setting the delaytimes can be eliminated and the circuit arrangement can be simplified.Accordingly, the manufacture is facilitated, and no change in the delaytimes are caused by change in temperature or with the lapse of time,resulting in an advantage that the maintenance can be made easy.

The need for the provision of a separate mode set-up means in the memorytesting apparatus can be eliminated by adopting a technique in which, inthe RAM testing mode, the pattern generator is previously set or aprogram is prepared for operating the pattern generator so that itgenerates a desired test pattern data, and data previously written inthe ROM expected value memory 16 are generated from the ROM expectedvalue memory 16 or fixed data all bits of which have the same logic aregenerated by control means, and in the ROM testing mode, the patterngenerator is previously set or a program is prepared for operating thepattern generator so that it generates fixed data all bits of which havethe same logic and the same data previously written in the ROM expectedvalue memory 16 as the data stored in the memory under test aregenerated from the ROM expected value memory 16. As a result, there areobtained advantages that the circuit arrangement can be farthersimplified and the manufacture can be further facilitated.

While the embodiment has been described above in connection with atesting of IC memory, it should be understood that the memory testingapparatus according to the present invention is also applicable totesting memories other than IC memory with similar functioning andeffect.

What is claimed is:
 1. A memory testing apparatus comprising:a patterngenerator for outputting at least an address pattern data and a testpattern data; a waveform generator for converting the address patterndata and the test pattern data outputted from said pattern generatorinto an address pattern signal and a test pattern signal each having areal waveform; means for applying the address pattern signal and thetest pattern signal outputted from said waveform generator to a memoryunder test; a ROM expected value memory for outputting a ROM expectedvalue pattern data in a ROM testing mode; a first logical comparator forlogically comparing a data read out of the memory under test with anexpected value pattern data outputted from said pattern generator in aRAM testing mode; a second logical comparator for logically comparing aresult of the logical comparison in said first logical comparator with adata outputted from said ROM expected value memory; and a failureanalysis memory having the same address area as that of the memory undertest for storing a failure data outputted from said second logicalcomparator at the same address as that of a memory cell in the memoryunder test where a failure has occurred, said memory testing apparatusbeing characterized in that in the RAM testing mode, fixed data all bitsof which have the same logic are outputted from said ROM expected valuememory to be supplied to said second logical comparator, and in the ROMtesting mode, fixed data all bits of which have the same logic areoutputted from said pattern generator to be supplied to said firstlogical comparator.
 2. The memory testing apparatus according to claim1, further comprising an analog comparator for determining whether ornot the logical value of a response output signal read out of the memoryunder test has a given voltage value, and wherein a data of thecomparison result in said analog comparator is supplied to said firstlogical comparator.
 3. The memory testing apparatus according to claim 1or claim 2, further comprising mode setting means which serves tosupply, in the RAM testing mode, fixed data all bits of which have thesame logic from said ROM expected value memory to said second logicalcomparator, and to supply, in the ROM testing mode, fixed data all bitsof which have the same logic from said pattern generator to said firstlogical comparator.
 4. The memory testing apparatus according to claim 1or claim 2, further comprising:pattern generator set-up means forsetting said pattern generator so that a predetermined pattern data isgenerated from said pattern generator in the RAM testing mode as well asfixed data all bits of which have the same logic are generated therefromin the ROM testing mode; and control means for controlling said ROMexpected value memory so that fixed data all bits of which have the samelogic are outputted from said ROM expected value memory in the RAMtesting mode as well as a ROM expected value pattern data previouslywritten therein is outputted therefrom in the ROM testing mode.
 5. Thememory testing apparatus according to claim 1 or claim 2, furthercomprising:programming means for programming said pattern generator sothat a predetermined pattern data is generated from said patterngenerator in the RAM testing mode as well as fixed data all bits ofwhich have the same logic are generated therefrom in the ROM testingmode; and control means for controlling said ROM expected value memoryso that fixed data all bits of which have the same logic are outputtedfrom said ROM expected value memory in the RAM testing mode as well as aROM expected value pattern data previously written therein is outputtedtherefrom in the ROM testing mode.
 6. The memory testing apparatusaccording to claim 1 or claim 2, wherein said pattern generator is setin the RAM testing mode such that a predetermined pattern data isgenerated from said pattern generator as well as fixed data previouslywritten in said ROM expected value memory, all bits of which have thesame logic, are generated from said ROM expected value memory, and saidpattern generator is set in the ROM testing mode such that fixed dataall bits of which have the same logic are outputted from said patterngenerator as well as a ROM expected value pattern data previouslywritten in said ROM expected value memory is outputted therefrom.
 7. Thememory testing apparatus according to claim 1 or claim 2, wherein inthee RAM testing mode, a program is prepared for operating said patterngenerator so that a predetermined pattern data is generated from saidpattern generator as well as fixed data previously written in said ROMexpected value memory, all bits of which have the same logic, aregenerated from said ROM expected value memory, and in the ROM testingmode, a program is prepared for operating said pattern generator so thatfixed data all bits of which have the same logic are outputted from saidpattern generator as well as a ROM expected value pattern datapreviously written in said ROM expected value memory is outputtedtherefrom.
 8. The memory testing apparatus according to claim 1, whereineach of said first and said second logical comparators outputs logical"0" when both the inputs thereto coincide with each other and outputslogical "1" when both the inputs thereto do not coincide with eachother.
 9. The memory testing apparatus according to claim 1, wherein thefixed data all bits of which have the same logic outputted from said ROMexpected value memory in the RAM testing mode comprise logical "0s", andthe fixed data all bits of which have the same logic outputted from saidpattern generator in the ROM testing mode also comprise logical "0s".10. The memory testing apparatus according to claim 1 or claim 2,wherein a first delay circuit is inserted in a transmission path for anaddress pattern data supplied from said pattern generator to saidfailure analysis memory, and a second delay circuit is inserted in atransmission path for an address pattern data supplied from said patterngenerator to said ROM expected value memory, said first delay circuithaving a delay time substantially equal to a time interval from the timepoint that an address pattern data is supplied to said waveformgenerator until the time point that a data read out of the memory undertest is logically compared in said first logical comparator and a resultof the logical comparison is outputted therefrom, said second delaycircuit having a delay time equal to a time interval in which a timeduration taken from the time point that said ROM expected value memoryis accessed and to the time point that the stored data is read outthereof is subtracted from said delay time of the first delay circuit.11. A method of switching the memory testing apparatus claimed in claim1 between the RAM testing mode and the ROM testing mode, comprising thesteps of:in the RAM testing mode, generating fixed data all bits ofwhich have the same logic from said ROM expected value memory withoutpreviously writing any data in said ROM expected value memory as well assetting said pattern generator to generate a RAM testing pattern datatherefrom; and in the ROM testing mode, generating a ROM testing patterndata previously written in said ROM expected value memory therefrom aswell as setting said pattern generator to generate fixed data all bitsof which have the same logic therefrom.
 12. A method of switching thememory testing apparatus claimed in claim 1 between the RAM testing modeand the ROM testing mode, comprising the steps of:in the RAM testingmode, generating fixed data previously written in said ROM expectedvalue memory, all bits of which have the same logic, therefrom as wellas setting said pattern generator to generate a RAM testing pattern datatherefrom; and in the ROM testing mode, generating a ROM testing patterndata previously written in said ROM expected value memory therefrom aswell as setting said pattern generator to generate fixed data all bitsof which have the same logic therefrom.
 13. A method of switching thememory testing apparatus claimed in claim 1 between the RAM testing modeand the ROM testing mode, comprising the steps of:in the RAM testingmode, generating fixed data all bits of which have the same logic fromsaid ROM expected value memory without previously writing any data insaid ROM expected value memory as well as generating a RAM testingpattern data from said pattern generator by means of a program foroperating said pattern generator; and in the ROM testing mode,generating a ROM testing pattern data previously written in said ROMexpected value memory therefrom as well as generating fixed data allbits of which have the same logic from said pattern generator by meansof a program for operating said pattern generator.
 14. A method ofswitching the memory testing apparatus claimed in claim 1 between theRAM testing mode and the ROM testing mode, comprising the steps of:inthe RAM testing mode, generating fixed data previously written in saidROM expected value memory, all bits of which have the same logic,therefrom as well as generating a RAM testing pattern data from saidpattern generator by means of a program for operating said patterngenerator; and in the ROM testing mode, generating a ROM testing patterndata previously written in said ROM expected value memory therefrom aswell as generating fixed data all bits of which have the same logic fromsaid pattern generator by means of a program for operating said patterngenerator.